1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device having at least two types of pillar-shaped insulated gate field effect transistors with different threshold characteristics on the same substrate.
2. Description of the Related Art
The pillar-shaped insulated gate field effect transistor (hereinafter referred to as pillar-FET) can increase a ratio between on-current and off-current by depleting a channel region and thus is suitable for low-voltage and high-speed operation. In a region with a pillar width of 100 nm or less, a characteristic improving effect due to depletion of the channel region is observed. Further decrease in pillar width leads to a further improvement in the ratio between on-current and off-current to be observed.
In addition, the pillar-FETs require various threshold voltages depending on circuit operation, which is controlled by changing an impurity concentration of the channel region in the same manner as ordinary planer FETs.
Examples of a method of diffusing an impurity into a channel region of a pillar-FET include a procedure disclosed in JP 2009-081377A, where in FIG. 2 to FIG. 12, and in paragraphs [0017] to [0027], a predetermined concentration of boron is diffused in a silicon substrate beforehand and then a silicon pillar is formed. However, the description focuses only on a single channel impurity concentration.
With improvement in the ratio between on-current and off-current caused by decrease in pillar width, a depletion region extends to an entire pillar of the channel region, resulting in reduction of the amount of change in threshold voltage corresponding to reduction of the amount of change in impurity concentration.
When the impurity concentration dependence of the amount of change in threshold voltage becomes too small, excessively high or low impurity concentration is required to obtain a desired threshold voltage. This may cause serious damage such as a reduction in source-to-drain punch-through breakdown voltage and a reduction in PN junction breakdown voltage.